In the future, memory modules may require in-Dynamic Random Access Memory (DRAM) error correction. Combined with the use of narrow channels, the overhead required for error correction may be increasing. For example, transitioning from wide channels to narrow channels may double the error correction overhead. Satisfying the reliability, availability, and serviceability (RAS) requirements for memory may become expensive. But discarding error correction capability entirely may reduce the usability of the memory module.
A need remains for a way for to provide error correction capability in a memory module without increasing the overhead requirements for error correction.